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LCD控制器方面留学生作业写作指导-LCD CONTROLLER--英国论文代写范文精选

2015-11-17 | 来源:51Due教员组 | 类别:更多范文

LCD控制器方面留学生作业写作指导-LCD CONTROLLER
 
15-1
OVERVIEW
The LCD controller in the S3C2410X consists of the logic for transferring LCD image data from a video buffer located in system memory to an external LCD driver. The LCD controller supports monochrome, 2-bit per pixel (4-level gray scale) or 4-bit per pixel (16-level grayscale) mode on a monochrome LCD, using a time-based dithering algorithm and Frame Rate Control (FRC)method and it can be interfaced with a color LCD panel at 8-bit per pixel (256-level color) and 12-bit per pixel(4096-level color) for interfacing with STN LCD.
It can support 1-bit per pixel, 2-bit per pixel, 4-bit per pixel, and 8-bit per pixel for interfacing with the palettized
TFT color LCD panel, and 16-bit per pixel and 24-bit per pixel for non-palettized true-color display.
The LCD controller can be programmed to support different requirements on the screen related to the number of horizontal and vertical pixels, data line width for the data interface, interface timing, and refresh rate.
FEATURES
STN LCD displays:
— Supports 3 types of LCD panels: 4-bit dual scan, 4-bit single scan, and 8-bit single scan display type
— Supports the monochrome, 4 gray levels, and 16 gray levels
— Supports 256 colors and 4096 colors for color STN LCD panel
— Supports multiple screen size
Typical actual screen size: 640480, 320240, 160160, and others
Maximum virtual screen size is 4Mbytes.
Maximum virtual screen size in 256 color mode: 40961024, 20482048, 10244096, and others
TFT LCD displays:
— Supports 1, 2, 4 or 8-bpp (bit per pixel) palettized color displays for TFT
— Supports 16-bpp non-palettized true-color displays for color TFT
— Supports 24-bpp non-palettized true-color displays for color TFT
— Supports maximum 16M color TFT at 24bit per pixel mode
— Supports multiple screen size
Typical actual screen size: 640480, 320240, 160160, and others
Maximum virtual screen size is 4Mbytes.
Maximum virtual screen size in 64K color mode: 20481024 and others
15-2
COMMON FEATURES
The LCD controller has a dedicated DMA that supports to fetch the image data from video buffer located in system memory. Its features also include:
— Dedicated interrupt functions (INT_FrSyn and INT_FiCnt)
— The system memory is used as the display memory.
— Supports Multiple Virtual Display Screen (Supports Hardware Horizontal/Vertical Scrolling)
— Programmable timing control for different display panels
— Supports little and big-endian byte ordering, as well as WinCE data formats(51Due责任编辑:admin)
— Supports SEC TFT LCD panel (SAMSUNG 3.5Portrait/256K Color/Reflective a-Si TFT LCD)
LTS350Q1-PD1: TFT LCD panel with touch panel and front light unit
LTS350Q1-PD2: TFT LCD panel only
NOTE
WinCE doesn't support the 12-bit packed data format.
Please check if WinCE can support the 12-bit color-mode.
EXTERNAL INTERFACE SIGNAL
VFRAME/VSYNC/STV : Frame synchronous signal (STN)/vertical synchronous signal (TFT)/SEC TFT signal
VLINE/HSYNC/CPV : Line synchronous pulse signal (STN)/horizontal sync signal (TFT)/SEC TFT signal
VCLK/LCD_HCLK : Pixel clock signal (STN/TFT)/SEC TFT signal
VD[23:0] : LCD pixel data output ports (STN/TFT/SEC TFT)
VM/VDEN/TP : AC bias signal for the LCD driver (STN)/data enable signal (TFT)/SEC TFT signal
LEND/STH : Line end signal (TFT)/SEC TFT signal
LCD_PWREN : LCD panel power enable control signal
LCDVF0 : SEC TFT Signal OE
LCDVF1 : SEC TFT Signal REV
LCDVF2 : SEC TFT Signal REVB
The 33 output ports in total includes 24 data bits and 9 control bits
15-3
BLOCK DIAGRAM
The S3C2410X LCD controller is used to transfer the video data and to generate the necessary control signals ,such as VFRAME, VLINE, VCLK, VM, and so on. In addition to the control signals, the S3C2410X has the data ports for video data, which are VD[23:0] as shown in Figure 15-1. The LCD controller consists of a REGBANK,LCDCDMA, VIDPRCS, TIMEGEN, and LPC3600 (See the Figure 15-1 LCD Controller Block Diagram). The REGBANK has 17 programmable register sets and 256x16 palette memory which are used to configure the LCD controller. The LCDCDMA is a dedicated DMA, which can transfer the video data in frame memory to LCD driver automatically. By using this special DMA, the video data can be displayed on the screen without CPU intervention. The VIDPRCS receives the video data from the LCDCDMA and sends the video data through the VD[23:0] data ports to the LCD driver after changing them into a suitable data format, for example 4/8-bit single scan or 4-bit dual scan display mode. The TIMEGEN consists of programmable logic to support the variable requirements of interface timing and rates commonly found in different LCD drivers. The TIMEGEN block generates VFRAME, VLINE, VCLK, VM, and so on.
 
 
Figure 15-1. LCD Controller Block Diagram
The description of data flow is as follows:
FIFO memory is present in the LCDCDMA. When FIFO is empty or partially empty, the LCDCDMA requests data fetching from the frame memory based on the burst memory transfer mode (consecutive memory fetching of 4 words (16 bytes) per one burst request without allowing the bus mastership to another bus master during the bus transfer). When the transfer request is accepted by bus arbitrator in the memory controller, there will be four successive word data transfers from system memory to internal FIFO. The total size of FIFO is 28 words, which consists of 12 words FIFOL and 16 words FIFOH, respectively. The S3C2410X has two FIFOs to support the dual scan display mode. In case of single scan mode, one of the FIFOs (FIFOH) can only be used.(51Due责任编辑:admin)
15-4
LCD CONTROLLER SPECIAL REGISTERS
LCD Control 1 Register
 
Register Address R/W Description Reset Value
LCDCON1 0X4D000000 R/W LCD control 1 register 0x00000000
 
LCDCON1 Bit Description Initial State
LINECNT
(read only) [27:18] Provide the status  of the line counter.
 Down count from LINEVAL to 0 0000000000
CLKVAL [17:8] Determine the rates of VCLK and CLKVAL[9:0].
STN: VCLK = HCLK / (CLKVAL * 2)
TFT: VCLK = HCLK / [(CLKVAL+1) * 2] 0000000000
MMODE [7] Determine the toggle rate of the VM.
0 = Each Frame,
1 = The rate defined by the MVAL 0
PNRMODE [6:5] Select the display mode.
00 = 4-bit dual scan display mode (STN)
01 = 4-bit single scan display mode (STN)
10 = 8-bit single scan display mode (STN)
11 = TFT LCD panel 00
BPPMODE [4:1] Select the BPP (Bits Per Pixel) mode.
0000 = 1 bpp for STN, Monochrome mode
0001 = 2 bpp for STN, 4-level gray mode
0010 = 4 bpp for STN, 16-level gray mode
0011 = 8 bpp for STN, color mode
0100 = 12 bpp for STN, color mode
1000 = 1 bpp for TFT
1001 = 2 bpp for TFT
1010 = 4 bpp for TFT(51Due责任编辑:admin)
1011 = 8 bpp for TFT
1100 = 16 bpp for TFT
1101 = 24 bpp for TFT 0000
ENVID [0] LCD video output and the logic enable/disable.
0 = Disable the video output and the LCD control signal.
1 = Enable the video output and the LCD control signal. 0
 
LCD Control 2 Register
 
Register Address R/W Description ReReset Value
LCDCON2 0X4D000004 R/W LCD control 2 register 0x00000000
 
 
LCDCON2 Bit Description Initial State
VBPD [31:24] TFT: Vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period.
STN: These bits should be set to zero on STN LCD. 0x00
LINEVAL [23:14] TFT/STN: These bits determine the vertical size of LCD panel. 0000000000
VFPD [13:6] TFT: Vertical front porch is the number of inactive lines at the end of a frame, before vertical synchronization period.
STN: These bits should be set to zero on STN LCD. 00000000
VSPW [5:0] TFT: Vertical sync pulse width determines the VSYNC pulse's high level width by counting the number of inactive lines.
STN: These bits should be set to zero on STN LCD. 000000
 
LCD Control 3 Register(51Due责任编辑:admin)
 
Register Address R/W Description Reset Value
LCDCON3 0X4D000008 R/W LCD control 3 register 0x00000000
 
 
LCDCON3 Bit Description Initial state
HBPD (TFT) [25:19] TFT: Horizontal back porch is the number of VCLK periods between the falling edge of HSYNC and the start of active data. 0000000
WDLY (STN) STN: WDLY[1:0] bits determine the delay between VLINE and VCLK by counting the number of the HCLK. WDLY[7:2] are reserved.
00 = 16 HCLK, 01 = 32 HCLK, 
10 = 48 HCLK, 11 = 64 HCLK
HOZVAL [18:8] TFT/STN: These bits determine the horizontal size of LCD panel.HOZVAL has to be determined to meet the condition that total bytes of 1 line are 4n bytes. If the x size of LCD is 120 dot in mono mode, x=120 cannot be supported because 1 line consists of 15 bytes. Instead, x=128 in mono mode can be supported because 1 line is composed of 16 bytes (2n). LCD panel driver will discard the additional 8 dot. 00000000000
HFPD (TFT) [7:0] TFT: Horizontal front porch is the number of VCLK periods between the end of active data and the rising edge of HSYNC. 0X00
LINEBLANK
(STN) STN: These bits indicate the blank time in one horizontal line duration time. These bits adjust the rate of the VLINE finely. The unit of LINEBLANK is HCLK X 8.
Ex) If the value of LINEBLANK is 10, the blank time is inserted to VCLK during 80 HCLK.
 
LCD Control 4 Register
(51Due责任编辑:admin)
       
Register Address R/W Description Reset Value
LCDCON4 0X4D00000C R/W LCD control 4 register 0x00000000
 
LCDCON4 Bit Description Initial state
MVAL [15:8] STN: These bit define the rate at which the VM signal will toggle if the MMODE bit is set to logic '1'. 0X00
HSPW(TFT) [7:0] TFT: Horizontal sync pulse width determines the HSYNC pulse's high level width by counting the number of the VCLK. 0X00
WLH(STN) STN: WLH[1:0] bits determine the VLINE pulse's high level width by counting the number of the HCLK.
WLH[7:2] are reserved.
00 = 16 HCLK, 01 = 32 HCLK,
10 = 48 HCLK, 11 = 64 HCLK
 
LCD Control 5 Register
 
Register Address R/W Description Reset Value
LCDCON5 0X4D000010 R/W LCD control 5 register 0x00000000
 
LCDCON5 Bit Description Initial state
Reserved (51Due责任编辑:admin)
[31:17] This bit is reserved and the value should be '0'. 0
VSTATUS [16:15] TFT: Vertical Status (read only).
00 = VSYNC  01 = BACK Porch
10 = ACTIVE 11 = FRONT Porch 00
HSTATUS [14:13] TFT: Horizontal Status (read only).
00 = HSYNC  01 = BACK Porch
10 = ACTIVE 11 = FRONT Porch 00
BPP24BL [12] TFT: This bit determines the order of 24 bpp video memory.
0 = LSB valid 1 = MSB Valid 0
FRM565 [11] TFT: This bit selects the format of 16 bpp output video data.
0 = 5:5:5:1 Format
1 = 5:6:5 Format 0
INVVCLK [10] STN/TFT: This bit controls the polarity of the VCLK active edge.
0 = The video data is fetched at VCLK falling edge
1 = The video data is fetched at VCLK rising edge 0
INVVLINE [9] STN/TFT: This bit indicates the VLINE/HSYNC pulse polarity.
0 = Normal 1 = Inverted 0
INVVFRAME [8] STN/TFT: This bit indicates the VFRAME/VSYNC pulse polarity.
0 = Normal 1 = Inverted 0
INVVD [7] STN/TFT: This bit indicates the VD (video data) pulse polarity.
0 = Normal 1 = VD is inverted. 0
INVVDEN [6] TFT: This bit indicates the VDEN signal polarity.(51Due责任编辑:admin)
0 = Normal 1 = Inverted 0
INVPWREN [5] STN/TFT: This bit indicates the PWREN signal polarity.
0 = Normal 1 = Inverted 0
INVLEND [4] TFT: This bit indicates the LEND signal polarity.
0 = Normal 1 = Inverted 0
PWREN [3] STN/TFT: LCD_PWREN output signal enable/disable.
0 = Disable PWREN signal
1 = Enable PWREN signal 0
ENLEND [2] TFT: LEND output signal enable/disable.
0 = Disable LEND signal
1 = Enable LEND signal 0
BSWP [1] STN/TFT: Byte swap control bit.
0 = Swap Disable
1 = Swap Enable 0
HWSWP [0] STN/TFT: Half-Word swap control bit.
0 = Swap Disable
1 = Swap Enable 0
 
 
 
附录二(翻译)
15 LCD控制器
15-1
概述
S3C2410X中的LCD控制器主要用来实现从位于内存中的视频缓冲到外部LCD驱动的逻辑转换。
该LCD控制器支持单色,2位每像素(4级灰度)或者4位每像素(16级灰度)模式的一个单色液晶显示器,使用基于时间的都得算法和帧速率控制(RFC)方法并且它可以和带有彩色液晶面板的8位每像素(256级彩色)和12位每像素(4096级彩色)接口的液晶显示器连接。
它可以支持1位每像素,2位每像素,4位每像素,和8位每像素的TFT彩色液晶面板,和16位每像素以及24位每像素的非调色板的真彩色显示。
该LCD控制器可以编程,以满足不同横向、纵向比,不同数据线宽度的接口,接口时序和刷新频率的显示器的需求。
特征:
LCD液晶显示器:
——支持三种类型的液晶面板:4位双扫面,4位单扫描,和8位单扫描显示类型(51Due责任编辑:admin)
——支持单色,4灰阶层次,16灰阶层次
——支持256色和4096色的CSTN彩色液晶面板
——支持多种屏幕尺寸
典型的实际屏幕尺寸:640*480,320*240,160*160和其他最大虚拟屏幕尺寸4Mbytes,256色模式大虚拟屏幕尺寸:4096*1024,2048*2048,1024*4096,以及其他。
TFT液晶显示器:
——支持1、2、4或者8位每像素的调色板彩色TFT显示器
——支持16位每像素非调色板真彩色TFT显示器
——支持24位每像素非调色板真彩色TFT显示器
——支持最大16M彩色TFT在24位每像素模式下
——支持多种屏幕尺寸
典型的实际屏幕尺寸:640*480,320*240,160*160,和其他最大虚拟屏幕是4Mbytes,在64K色模式下最大虚拟屏幕是2048*1024和其它。
 
15-2
共同特点
该LCD控制器拥有专用的DMA用来从位于系统内存中的视频缓冲区获取图像数据,它的功能还包括:
——专用中断功能(TNT_FrSyn 和 INT_FiCnt)
——系统内存作为显示内存
——支持多个虚拟现实屏幕(支持硬件水平/垂直滚动)
——可编程定时控制不同的显示面板
——支持小和大端字节序,以及嵌入式数据格式
——支持SEC TFT液晶面板(三星3.5英寸/256K色/反射的 TFT 液晶显示器)
LTS350Q1-PD1:TFT液晶面板的触摸屏和前灯组
LTS350Q1-PD2:TFT液晶面板
注意:
嵌入式不支持12位便携数据格式,请检查嵌入式是否支持12位彩色显示模式。
外部接口信号:
VFRAME/VSYNC/STV :帧同步信号(LCD)/垂直同步信号(TFT)/第二TFT信号
VLINE/HSYNC/CPV:行同步信号(STN)/水平同步信号(TFT)/第二TFT信号
VCLK/LCD_HCLK::像素时钟信号(STN/TFT)/第二TFT信号
VD[23:0]:LCD像素输出端口(STN/TFT/SEC TFT)
VM/VDEN/TP:交流偏置信号的LCD驱动(STN)/数据使能信号(TFT)/第二TFT信号
LEND/STH:结束信号(TFT)/第二TFT信号
LCD_PWREN:LCD电源控制信号
LCDVF0:第二TFT光电信号
LCDVF1:第二TFT翻转信号
LCDVF2:第二TFTR EVB信号
33位输出端口包括24位数据端口和9位控制端口
 
15-3
框图
 
图 15-1 LCD 控制器框图
 
S3C2410X的LCD控制器是用来传输视频数据和产生必要的控制信号,例如VFRAME、VLINE、VCLK、VM等等。除了这些控制信号,S3C2410X有数据端口传输视频数据,VD[23:0]如图15-1所示。在该LCD控制器由寄存器组(REGBANK)、DMA通道(LCDCDMA)、时序信号发生器(TIMEGEN)、时序控制单元(LPC3600)、视频信号处理(VIDPRCS)。在寄存器组中有17个可编程寄存器和256*16的调色板存储器来配置LCD控制器。DMA通道是一个专用DMA,它可以自动将视频数据帧存储器中等的视频数据到LCD驱动器。通过使用这个特殊的MDA,视频数据可以显示在屏幕上无需CPU干预。视频信号处理器从DMA通道接收视频数据,改变成一个适合的数据格式,例如4/8位单扫描或者4位双扫描模式,之后通过VD[23:0]数据接口传输到LCD驱动器。时序信号发生器包含可编程逻辑支持对于接口时序、刷新频率的不同LCD驱动器的要求。该模块生成VFRAME,VLINE,VCLK,VM等。数据流的描述如下:DMA通道包含FIFO的内存模块。当FIFO模块中的数据空或者部分空时,DMA通道请求数据并从帧内存存储器基于突发内存传输模式(每次突发请求连续取4字(16位),在总线传输时不允许转让总线使用权)当转让的请求被内存控制器中的总线仲裁机构接受,将有四个字的连续数据从系统内存传输到FIFO模块。FIFO模块的大小为28个字,分别是12个字的FIFIOL和16个字的FIFOH。S3C2410X中有2个FIFO模块去支持双扫描显示模块。如果在单扫描显示模式,只能使用其中的一个FIFO模块(FIFOH)。(51Due责任编辑:admin)
 
15-4
LCD控制器特殊寄存器
LCD控制器 寄存器1
寄存器 地址 读/写 描述 复位值
LCDCON1 0x4D000000 读/写 LCD控制器寄存器1 0x00000000
 
LCDCON1 位 描述 初始状态
LINECNT
(只读) [27:18] 提供计数状态
从LINEVAL减到0 0000000000
CLKVAL [17:8] 决定VCLK和CLKVAL[9:0]的值
STN:VCLK=HCLK/(CLKVAL*2)
TFT:VCLK=HCLK/[(CLKVAL+1)*2] 0000000000
MMODE [7] 决定VM的切换平率
0=每帧
1=由MVAL确定的值 0
PNRMODE [6:5] Select the display mode
00=4位双扫描模式
01=4位单扫描模式
10=8位单扫描模式
11=TFT 液晶面板 00
BPPMDOE [4:1] 选择每像素位模式
0000=1位每像素(STN),黑白模式
0001=2位每像素(STN),4级灰度
0010=4位每像素(STN),16级灰度
0011=8位每像素(STN),彩色模式
0100=12位每像素(STN),彩色模式
1000=1位每像素(TFT)
1001=2位每像素(TFT)
1010=4位每像素(TFT)
1011=8位每像素(TFT)
1100=16位每像素(TFT)
1101=24位每像素(TFT) 0000
ENVID (51Due责任编辑:admin)
[0] LCD视频输出的启用/禁用
0=不允许视频输出和LCD控制信号
1=允许视频输出和LCD控制信号 0
LCD控制器寄存器2
寄存器 地址 读/写 描述 复位值
LCDCON2 0x4D000004 读/写 LCD控制寄存器2 0x00000000
 
LCDCON2 Bit 描述 Initial State
VBPD [31:24] TFT:在垂直同步以后,垂直后门廊是在一帧的开始时的无效行数
STN:设置为0 0x00
LINEVAL [23:14] 这些位确定液晶面板的垂直尺寸 0000000000
VFPD [13:6] TFT:在垂直同步以前,垂直前门廊是在一帧的结束时的无效行数
STN:设置为0 00000000
VSPW [5:0] TFT:垂直同步脉冲宽度确定VSYNC脉冲的高水平宽度通过计数无效行的数目。
STN:设置为0 000000
 
LCD 控制器寄存器3
寄存器 地址 读/写 描述 复位值
LCDCON3 0x4D000008 读/写 LCD控制寄存器3 (51Due责任编辑:admin)
0x00000000
 
LCDCON3 位 描述 初始值
HBPD(TFT) [25:19] TFT: 卧式后门廊是一些VCLK时期在下降沿的HSYNC和有效数据开始之间 0000000
 
WDLY(STN) STN:WDLY[1:0]位决定VLINE和VCLK之间的延迟通过计数HCLK。WDLY[7:2]保留。
00=16HCLK,01=32HCLK,10=48HCLK,11=64HCLK
HOZVAL [18:8] TFT/STN:这些位数决定液晶面板的横向尺寸,HOZVAL被确定满足1行的总字节数是4的倍数。如果LCD的X尺寸是120在单色模式下,x=120将不被支持因为1行包含15个字节,x=128在单色模式下将被支持,因为一行包含16个字节(2的倍数)。液晶面板驱动器将抛弃额外的8点 00000000000
HFPD(TFT) [7:0] TFT: 卧式前门廊是一些VCLK时期在上升沿的HSYNC和有效数据结束之间 0x00
LINEBLANK STN:这些位表明空白时间显示在一个水平线持续时间。这些位精确的调整VLINE的值。LINEBLANK的单位是HCLK*8.(如果LINEBLANK的值是10,空白时间在80HCLK被插入到VCLK)
 
LCD控制器 寄存器4
寄存器 地址 读/写 描述 复位值
LCDCON4 0x4D00000C 读/写 LCD控制寄存器4 0x00000000
 
LCDCON4 位 描述 初始值
MVAL (51Due责任编辑:admin)
[15:8] STN:这些位定义VM信号的切换值,如果MMODE位被设置为‘1’ 0X00
HSPW(TFT) [7:0] TFT: 水平同步脉冲宽度确定HSYNC脉冲的高度宽度通过计数VCLK 数目。 0X00
WLH(STN) STN:WLH[1:0]位决定VLINE脉冲的高度宽度通过计数HCLK的数目。
WLH[7:2]保留
00 = 16 HCLK, 01 = 32 HCLK,
10 = 48 HCLK, 11 = 64 HCLK
 
LCD控制器 寄存器5
 
寄存器 地址 读/写 描述 复位值
LCDCON5 0x4D000010 读/写 LCD控制寄存器5 0x00000000
 
 
LCDCON5 位 描述 初始值
保留 [31:17] 这些位保留且值为0 0
VSTATUS [16:15] TFT:垂直状态(只读)
00=VSYNC  01=BACK Porch
10=ACTIVE 11=FRONT Porch 00
HSTATUS [14:13] TFT:水平状态(只读)
00=VSYNC  01=BACK Porch
10=ACTIVE 11=FRONT Porch 00
BPP24BL [12] TFT:这位决定了24位每像素视频内存的格式
0=最低为有效 1=最高为有效 0
FRM565 [11] TFT:这位选择16位每像素输出视频数据的顺序
0=5:5:5:1格式   1=5:6:5格式 0
INVVCLK [10] STN/TFT:这位控制VCLK的有效边缘
0=视频数据获取在VCLK下降沿
1=视频数据获取在VCLK上升沿 0
INVVLINE [9] STN/TFT:这为表明VLINE/HSYNC
的脉冲极性
0=正常
1=颠倒 0
INVVFRAME [8] STN/TFT:这位表明VFRAME/VSYNC的脉冲极性
0=正常
1=颠倒 0
INVVD [7] STN/TFT:这位表明视频数据的脉冲极性
0=正常
1=视频数据颠倒 0
INVVDEN [6] TFT:这位表明VDEN信号极性
0=正常
1=颠倒 0
INVPWREN [5] TFT:这位表明PWREN信号极性
0=正常
1=颠倒 0
INVLEND [4] TFT:这位表明LEND信号极性
0=正常
1=颠倒 0
PWREN [3] STN/TFT:这位表明LCD_POWREN输出信号信启用/禁用
0=启用
1=禁用 0
ENLEND [2] STN/TFT:这位表明LEND输出信号信启用/禁用
0=启用
1=禁用 0
BSWP [1] STN/TFT:字节交换控制位
0=交换启用
1=交换禁用 0
HWSWP [0] STN/TFT:半字交换控制位
0=交换启用
1=交换禁用 0
 
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